Optimized for Automotive Audio: SHARC+ and Audio Weaver
In a collaboration between DSP Concepts and Analog Devices, the performance of Audio Weaver® Core runtime libraries has been optimized to take full advantage of the SHARC+® core and to leverage the powerful SHARC+ DSP FIR/IIR hardware accelerators.
This optimization effort results in tangible benefits for developers of automotive audio systems and other products, when utilizing audio processors in the ADSP-2156x, ADSP-2159x, and ADSP-SC59x product families. With more efficient use of the Audio Weaver embedded libraries, CPU load is decreased in many cases, allowing processing headroom to support more complex algorithms when using Audio Weaver.
First, a tour of the tools and technology…
DSP Concepts has focused on the embedded Audio Weaver Core runtime libraries, which contain the collection of processing modules. Both standard and advanced DSP modules have been optimized for the SHARC+ cores, exhibiting significant improvement in CPU load.
Analog Devices has made improvements to the AWE Core libraries to use FIR/IIR assembly optimized to make best use of the 11-stage pipeline of the SHARC+ core and to leverage the FIR/IIR hardware accelerators wherever possible. Additionally, the optimized AWE Core has incorporated Analog Devices’ statistics functions, optimized math functions, and a host of hand-optimized DSP libraries such as complex and real Fast Fourier Transform (FFT) algorithms.
As a result of this effort, AWE Core libraries running on SHARC+ processor cores exhibit increased efficiency that can reduce overall CPU load, providing more overhead for additional features or increased channel counts. For example, comparing ADSP-21569 benchmarks before and after optimization shows an appreciable improvement. A stark contrast can be observed in designs utilizing FIR or Biquad filter modules instantiated across high channel counts, with a potential increase in processing headroom of more than 13%.
Figure 1: Optimized Library General Performance Gains
The real-world performance gains of the Audio Weaver optimization for SHARC+ cores are realized due to the increased headroom for processing, allowing more work to be offloaded to the DSP in an automotive system. These gains are demonstrated with example layouts running on an ADSP-21569 processor, shown below. The following images depict the three most MIPS-intense modules in example audio levels 1 (ALEV1) and 2 (ALEV2).
Figure 2: ALEV1 Performance Gains
Figure 3: ALEV2 Performance Gains
The IIR hardware accelerator (one MAC unit) realized more than a 20% efficiency improvement, and using the ADI DSP library code provided additional MIPS savings. Additional IIR improvements can be achieved with ADSP-2159x or ADSP-SC59x processors, as each SHARC+ core features four IIR engines (one MAC unit in each).
For automotive audio system design, the newly optimized AWE Core libraries and SHARC+ processor cores provide a significant advantage to developers. This combination of tools helps streamline the development process, and the joint optimization effort by DSP Concepts and Analog Devices demonstrates real-world results that help product makers create competitive, feature-rich designs.